Memory cells in a DRAM device include a transistor and a capacitor to store a bit of data. The memory cells are ‘dynamic’ because their data decays and becomes invalid due to various leakage current paths to surrounding cells and to the substrate of the device. To keep the data in the cells valid, each memory cell is periodically refreshed.
Every row of cells in a DRAM memory array needs to be refreshed before the data in the row decays to an invalid state. There are two types of refreshes: external refreshes and internal refreshes (i.e., the DRAM device places itself in self-refresh mode).
During internal DRAM memory refreshes, the memory controller has no visibility to when this refresh is initiated. As a result, the controller is designed to wait for an entire refresh cycle (tRFC, plus a guard band, e.g., 10 ns) before issuing a command to the DRAM. The time period a memory controller must wait before issuing a valid command is herein referred to as tXS (i.e., tRFC+10 ns). tRFC for a 2 Gbit device is in the range of 160 ns. The tRFC approximately doubles as DRAM devices increase in density (e.g., tRFC for a 4 GBit device is in the range of 300 ns, tRFC for an 8 Gbit device is in the range of 550 ns), thus increasing tXS.
Therefore it is desirable to reduce the value of tXS for DRAM devices in order to reduce the time a memory controller must wait before issuing valid commands.
Descriptions of certain details and implementations follow, including a description of the figures, which may depict some or all of the embodiments described below, as well as a discussion of other potential embodiments or implementations of the inventive concepts presented herein. An overview of embodiments of the invention is provided below, followed by a more detailed description with reference to the drawings.